Pipelined analog-to-digital converters (ADCs) are commonly used for data conversions at high frequencies. These pipelines often include several stages that each resolve a certain number of bits. Generally, a larger number of bits is resolved by the first stage of a pipeline, allowing for fewer stages to be employed. This is generally desirable because the reduction of the total number of stages usually reduces power consumption and usually improves the Spurious-Free Dynamic Range (SFDR). Flash/comparator and amplifier offset, though, usually limit the number of bits that the first stage can resolve, which ultimately results in a limited closed loop residue gain that affects the noise contribution of the first stage and the following stages.
Some examples of conventional designs are: U.S. Pat. Nos. 6,184,809; 6,195,032; 6,977,604; 7,002,507; 7,084,803; 7,095,352; 7,119,729; 7,173,556; 7,187,311; 7,289,055; PCT Publ. No. WO2001095494; Mathur et al., “Designing 1 MHz to 5 MHz conversion rate ADCs,” Electronics Engineer, May 1999; and Datasheet for Texas Instruments Incorporated's TLV1562 dated September 1998.